1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically to a semiconductor device having a complementary MOS (CMOS) and a method of manufacturing the same.
2. Description of the Prior Art
As a semiconductor integrated circuit device becomes larger in scale, an LSI in which a high speed logic circuit and a mass storage unit are mounted on the same semiconductor chip is in general use. In order to achieve high speed operation of a large capacity semiconductor integrated circuit, it is most effective to miniaturize a MOS transistor so as to improve the performance thereof and (metal oxide semiconductor) to increase an integration degree by miniaturization. Furthermore, it is effective as a countermeasure for the reduction of parasitic components to lower the resistance of a gate electrode of the MOS transistor and to lower the resistance of a source/drain diffused layer effectively. Further, it also produces an effect to increase the integration degree and to shorten a mean interconnection length by increasing interconnection density.
On the other hand, an SRAM cell using six MOS transistors is used frequently as the memory of a device of this sort, and it is desired to reduce the cell area for the purpose of achieving a large capacity in this device.
The improvement of basic performance of a MOS transistor follows a scaling rule, and has been achieved by reduction in the measurements of a plane component and reduction of the thickness of a diffused layer located in a depth direction.
As to the reduction of the resistance of the gate electrode of a MOS transistor, a salicide technique in which refractory metal silicide and polysilicon are laminated one upon another, and the refractory metal silicide is formed in a self-align manner on a polycide gate obtained by applying patterning to the lamination or polysilicon is known.
Further, as to the effective reduction of the resistance of the source/drain diffused layer, a salicide technique in which refractory metal silicide is formed in a self-align manner on a diffused layer or a technique in which a metal film is formed on the diffused layer selectively by a chemical vapor deposition method is known.
Furthermore, in order to increase the interconnection density, a technique for interconnection without an interlayer insulating film instead of contacting interconnections through an opening portion of the interlayer insulating film, i.e., what is called a local interconnection technique is known. This technique is also used for the SRAM cell, thereby aiming at reduction of the cell area.
Further, as to a p-channel MOS transistor, it has become necessary to use a surface channel type in which a gate electrode composed of p-type polysilicon is used, but, in a gate electrode in which silicide is formed in the upper part as described above, impurities inside thereof are liable to be diffused in a lateral direction.
Furthermore, since the p-type MOS transistor and the n-type MOS transistor are formed in an n-well and a p-well, respectively, these transistors are arranged separately, and the space therebetween becomes larger, which is conspicuous in particular in an SRAM cell. In this case, a method of connecting the p-type gate electrode of the p-type MOS transistor and the gate electrode composed of n-type polysilicon of the n-type MOS transistor to each other by local interconnection is known.
For example, the local interconnection is set forth in the US Patent Publication U.S. Pat. No. 4,821,085 and the method of forming the local interconnection is disclosed in U.S. Pat. No. 4,804,636 and U.S. Pat. No. 4,793,896. Further, an SRAM utilizing the local interconnection is disclosed in U.S. Pat. No. 4,804,636 and U.S. Pat. No. 4,975,756. Furthermore, that in which a p.sup.+ type gate electrode and an n.sup.+ type gate electrode are connected by local interconnection is set forth in U.S. Pat. No. 4,804,636 and U.S. Pat. No. 4,890,141.
The local interconnection has such a construction as shown in FIG. 1 for instance.
In FIG. 1, a transistor 3 is formed in a region surrounded by a field insulating film 2 on a semiconductor substrate 1, and an interconnection 4 is formed on the field insulating film 2. Further, in case a drain layer 5 of the transistor 3 and the interconnection 4 are connected to each other by local interconnection, after a titanium nitride film 8 is formed along the surfaces of the field insulating film 2, a gate electrode 6, a drain layer 5 and a source layer 7, patterning is applied to the titanium nitride film so as to leave the titanium nitride film 8 in a part from the drain layer 5 of the transistor 3 over to the interconnection. 4, which is used as a local interconnection 9.
Besides, a titanium silicide layer 10 formed by a salicide technique is formed on the surfaces of the gate electrode 6, the drain layer 5 and the source layer 7.
Now, when patterning is applied to the titanium nitride film 8 in order to form the local interconnection 9, the titanium nitride film 8 located on the gate electrode 6 and the source layer 7 is removed by etching.
With the advance of the miniaturization of a semiconductor device, however, a titanium silicide layer 10 formed by the salicide technique gets thinner. Therefore, etching selectivity between the titanium silicide layer 10 and the titanium nitride film 8 used for local interconnection has become insufficient. Accordingly, the local interconnection 9 having the construction described above cannot be applied to a refined semiconductor device.
Further, when a polycide film composed of tungsten silicide and polysilicon is used as a forming film of the gate electrode 6, the local interconnection 9 described above cannot be used for the titanium nitride film 8 since it has no etching selectivity for tungsten silicide.
In order to improve the performance of a fine transistor and to control parasitic components thereby to achieve a high speed of a logic circuit, a tungsten polycide gate or a salicide gate obtained by forming titanium silicide is required. At the same time, it is required to improve the integration degree of a semiconductor device such as an SRAM, but such is the present state of affairs that the accuracy of the pattern configuration of the local interconnection has not been improved sufficiently.
Further, in the Japanese Patent Provisional Publication No. SHO59-121868, a structure in that a molybdenum silicide pattern for connecting a diffused layer to an interconnection layer in an opening portion of an insulating film is provided, and this pattern is extended to another opening portion through above the insulating film is described. However, it is impossible to obtain sufficient flatness in a multi-layer structure with such a structure as described above.